IEEE Transactions on Software Engineering
Scheduling tests for VLSI systems under power constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 39th annual Design Automation Conference
On Concurrent Test of Core-Based SOC Design
Journal of Electronic Testing: Theory and Applications
Adaptive Test Scheduling in SoC's by Dynamic Partitioning
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Recent Advances in Test Planning for Modular Testing of Core-Based SOCs
ATS '02 Proceedings of the 11th Asian Test Symposium
Verification of Transaction-Level SystemC models using RTL Testbenches
MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
Power Constrained Test Scheduling with Dynamically Varied TAM
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
An ILP Formulation to Optimize Test Access Mechanism in System-on-Chip Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D
ATS '01 Proceedings of the 10th Asian Test Symposium
Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Power-Time Tradeoff in Test Scheduling for SoCs
ICCD '03 Proceedings of the 21st International Conference on Computer Design
FITS: An Integrated ILP-Based Test Scheduling Environment
IEEE Transactions on Computers
X-Gen: a random test-case generator for systems and SoCs
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Scheduling of transactions for system-level test-case generation
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Romeo: a tool for analyzing time petri nets
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Test scheduling for core-based systems using mixed-integer linear programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The effective scheduling of transactions has a great potential for SoC functional verification. Petri nets have proven to be a promising technique for solving scheduling problem. This paper aims at presenting a Petri-net based approach to the scheduling of transactions generated by a test-case generator. Firstly, an extended scheduling timed Petri nets (ESTPN) model is given to support transaction scheduling. Secondly, the short term of ‘scheduling of transactions problem' is formulated by means of an ESTPN which can accommodate various scheduling policies. Finally, transactions scheduling schemes and scheduling algorithm based on ESTPN are given and cases are studied