FITS: An Integrated ILP-Based Test Scheduling Environment
IEEE Transactions on Computers
Analysis of the test data volume reduction benefit of modular SOC testing
Proceedings of the conference on Design, automation and test in Europe
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
SOC test planning using virtual test access architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
Challenges for Semiconductor Test Engineering: A Review Paper
Journal of Electronic Testing: Theory and Applications
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Test planning for core-based system-on-a-chip (SOC) designs necessary to reduce testing time and test cost. In this paper, we sur-veyrecent advances in test planning that address the problems of access and constrained test scheduling for core-based SOCs. We describeseveral test access architectures proposed by research groupsin industry and academia, as well as a wide range of methodologiesfor the optimization of such architectures. An extensive list of referencesto prior and current work in the SOC test planning domain included.