On IEEE P1500's Standard for Embedded Core Test
Journal of Electronic Testing: Theory and Applications
Scan chain design for test time reduction in core-based ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Recent Advances in Test Planning for Modular Testing of Core-Based SOCs
ATS '02 Proceedings of the 11th Asian Test Symposium
On Using IEEE P1500 SECT for Test Plug-n-Play
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Set of Benchmarks fo Modular Testing of SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Test Scheduling and Scan-Chain Division under Power Constraint
ATS '01 Proceedings of the 10th Asian Test Symposium
Efficient Wrapper/TAM Co-Optimization for Large SOCs
Proceedings of the conference on Design, automation and test in Europe
Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
SOC test architecture design for efficient utilization of test bandwidth
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test Scheduling for Modular SOCs in an Abort-on-Fail Environment
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores
ITC '04 Proceedings of the International Test Conference on International Test Conference
Integrating Core Selection in the SOC Test Solution Design-Flow
ITC '04 Proceedings of the International Test Conference on International Test Conference
Hierarchy-aware and area-efficient test infrastructure design for core-based system chips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A non-intrusive isolation approach for soft cores
Proceedings of the conference on Design, automation and test in Europe
Challenges in testing core-based system ICs
IEEE Communications Magazine
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Modular SOC testing offers numerous benefits that include test power reduction, ease of timing closure, and test re-use among many others. While all these benefits have been emphasized by researchers, the test time and data volume comparisons has been mostly constrained within the context of modular SOC testing only, by comparing the impact of various different modular SOC testing techniques to each other. In this paper, we provide a theoretical test data volume analysis that compares the monolithic test of a flattened design with the same design tested in a modular manner; we present numerous experiments that gauge the magnitude of this benefit. We show that the test data volume reduction delivered by modular SOC testing directly hinges on the test pattern count variation across different modules, and that this reduction can exceed 99% in the SOC benchmarks that we have experimented with.