Proceedings of the 39th annual Design Automation Conference
On IEEE P1500's Standard for Embedded Core Test
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Computers
Power-aware SoC test planning for effective utilization of port-scalable testers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Analysis of the test data volume reduction benefit of modular SOC testing
Proceedings of the conference on Design, automation and test in Europe
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Microprocessor based self schedule and parallel BIST for system-on-a-chip
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
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An integrated technique for test scheduling and scan-chain division under power constraints is proposed in this paper. We demonstrate that optimal test time can be achieved for systems tested by an arbitrary number of tests per core using scan-chain division and we define an algorithm for it. The design of wrappers to allow different lengths of scan-chains per core is also outlined. We investigate the practical limitations of such wrapper design and make a worst case analysis that motivates our integrated test scheduling and scan-chain division algorithm. The efficiency and usefulness of our approach have been demonstrated with anindustrial design.