Microprocessor based self schedule and parallel BIST for system-on-a-chip

Authors:
Danghui Wang;Xiaoya Fan;Deyuan Gao;Shengbing Zhang;Jianfeng An
Affiliations:
Aviation Microelectronic Center, Northwestern Polytechnical University, Xi’an, P.R. China;Aviation Microelectronic Center, Northwestern Polytechnical University, Xi’an, P.R. China;Aviation Microelectronic Center, Northwestern Polytechnical University, Xi’an, P.R. China;Aviation Microelectronic Center, Northwestern Polytechnical University, Xi’an, P.R. China;Aviation Microelectronic Center, Northwestern Polytechnical University, Xi’an, P.R. China
Venue:
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Year:
2005

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Abstract

The purpose of this paper is to develop a flexible test method with high efficiency for core-based system-on-a-chip (SOC). The novel feature of the approach is the use of an embedded microprocessor/memory pair to test the remaining components of SOCs. The characteristics are: (1) Several IP cores can be tested in parallel; (2) The order of test tasks need not to be queued during test integration, but scheduled by test program. It is called microprocessor based self schedule and parallel BIST for SOC (MBSSP-BIST). By analyzing the bandwidth of test data, the feasibility of MBSSP-BIST is proved. Finally, several SOCs in ITC’02 benchmark are used to verify the approach and the results show that MBSSP-BIST can improve test efficiency significantly.