Proceedings of the 39th annual Design Automation Conference
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers
Proceedings of the 40th annual Design Automation Conference
Genetic Algorithm based Test Scheduling and Test Access Mechanism Design for System-on-Chips
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips
Journal of Electronic Testing: Theory and Applications
SOC test architecture design for efficient utilization of test bandwidth
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design of reconfigurable access wrappers for embedded core based SoC test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
A Graph-Based Approach to Power-Constrained SOC Test Scheduling
Journal of Electronic Testing: Theory and Applications
TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Searching for Global Test Costs Optimization in Core-Based Systems
Journal of Electronic Testing: Theory and Applications
Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Reusing an on-chip network for the test of core-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs
IEEE Transactions on Computers
Reuse-based test access and integrated test scheduling for network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Multiple-constraint driven system-on-chip test time optimization
Journal of Electronic Testing: Theory and Applications
System-on-chip test scheduling with reconfigurable core wrappers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modular and rapid testing of SOCs with unwrapped logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A System-layer Infrastructure for SoC Diagnosis
Journal of Electronic Testing: Theory and Applications
Analysis of the test data volume reduction benefit of modular SOC testing
Proceedings of the conference on Design, automation and test in Europe
The efficient TAM design for core-based SOCs testing
WSEAS Transactions on Circuits and Systems
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
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Core test wrappers and test access mechanisms (TAMs) are importantcomponents of a system-on-chip (SOC) test architecture.Wrapper/TAM co-optimization is necessary to minimize the SOC testingtime. Most prior research in wrapper/TAM design has addressedwrapper design and TAM optimization as separate problems, therebyleading to results that are sub-optimal. We present a fast heuristictechnique for wrapper/TAM co-optimization, and demonstrate itsscalability for several industrial SOCs. This extends recent work onexact methods for wrapper/TAM co-optimization based on integer linearprogramming and exhaustive enumeration. We show that the SOCtesting times obtained using the new heuristic algorithm are comparableto the testing times obtained using exact methods. Moreover,more than two orders of magnitude reduction can be obtained in theCPU time compared to exact methods. Furthermore, we are nowable to design efficient test access architectures with a larger numberof TAMs.