Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Genetic Algorithm based Test Scheduling and Test Access Mechanism Design for System-on-Chips
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Efficient Wrapper/TAM Co-Optimization for Large SOCs
Proceedings of the conference on Design, automation and test in Europe
Modelling and verification of delay-insensitive circuits using CCS and the concurrency workbench
Information Processing Letters
A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Adding Testability to an Asynchronous Interconnect for GALS SoC
ATS '04 Proceedings of the 13th Asian Test Symposium
A behavioral synthesis system for asynchronous circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SOC Testing Methodology and Practice
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
SOC test planning using virtual test access architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Testing of core-based systems-on-a-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Testing ASICs with multiple identical cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient test solutions for core-based designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Test Methodologies for Globally Asynchronous Locally Synchronous (GALS) System On a Chip (SOC) are a subject of growing research interest since they appear to offer benefits in low power applications and promise greater design modularity. Pre-designed cores and reusable modules are popularly used in the design of large and complex Systems. As the size and complexity of System increase, the test effort, including test development effort, test data volume, and test application time, has also significantly increased. Available techniques for testing of core-based systems on a chip do not provide a systematic means for compact test solutions. A test solution for a complex system requires good optimization of Test Scheduling and Test Access Mechanism (TAM). In this paper, we provide a Test Scheduling Optimization for Globally Asynchronous Locally Synchronous System-On-Chip Using Genetic Algorithm that gives compact test scheduling.