Modelling and verification of delay-insensitive circuits using CCS and the concurrency workbench

Authors:
Hemangee K. Kapoor;Mark B. Josephs
Affiliations:
Centre for Concurrent Systems and VLSI, Faculty of BCIM, London South Bank University, 103 Borough Road, London SE1 0AA, UK;Centre for Concurrent Systems and VLSI, Faculty of BCIM, London South Bank University, 103 Borough Road, London SE1 0AA, UK
Venue:
Information Processing Letters
Year:
2004

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Abstract

The modelling of delay-insensitive asynchronous circuits in the process calculus CCS is addressed. MUST-testing (rather than bisimulation) is found to support verification both of file property of delay-insensitivity and of design by stepwise refinement. Automated verification is possible with a well-known tool, the Edinburgh Concurrency Workbench.