Reuse methodology manual: for system-on-a-chip designs
Reuse methodology manual: for system-on-a-chip designs
Design of system-on-a-chip test access architectures under place-and-route and power constraints
Proceedings of the 37th Annual Design Automation Conference
Optimal test access architectures for system-on-a-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test Requirements for Embedded Core-Based Systems and IEEE P1500
Proceedings of the IEEE International Test Conference
Scan chain design for test time reduction in core-based ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
CTL the language for describing core-based test
Proceedings of the IEEE International Test Conference 2001
Test wrapper and test access mechanism co-optimization for system-on-chip
Proceedings of the IEEE International Test Conference 2001
On Using IEEE P1500 SECT for Test Plug-n-Play
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Wrapper Design for Embedded Core Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Efficient Wrapper/TAM Co-Optimization for Large SOCs
Proceedings of the conference on Design, automation and test in Europe
On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
A low overhead design for testability and test generation technique for core-based systems-on-a-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test scheduling for core-based systems using mixed-integer linear programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Formulating SoC test scheduling as a network transportation problem
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
InTeRail: A Test Architecture for Core-Based SOCs
IEEE Transactions on Computers
System-on-chip test scheduling with reconfigurable core wrappers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test cost reduction for SoC using a combined approach to test data compression and test scheduling
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2009 International Conference on Computer-Aided Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Testing of embedded core based system-on-chip (SoC) ICs is a well known problem, and the upcoming IEEE P1500 Standard on Embedded Core Test (SECT) standard proposes DfT solutions to alleviate it. One of the proposals is to provide every core in the SoC with test access wrappers. Previous approaches to the problem of wrapper design have proposed static core wrappers, which are designed for a fixed test access mechanism (TAM) width. We present the first report of a design of reconfigurable core wrappers which allow for a dynamic change in the width of the TAM executing the core test. Analysis of the corresponding scheduling problem indicates that good approximate schedules can be achieved without significant computational effort. Specifically, we derive a O(Nc2B) time algorithm which can compute near optimal SoC test schedules, where Nc is the number of cores and B is the number of top level TAMs. Experimental results on benchmark SoCs are presented which improve upon integer programming based methods, not only in the quality of the schedule, but also significantly reduce the computation time.