Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Tutorial on semiconductor memory testing
Journal of Electronic Testing: Theory and Applications - Special issue: on memory testing
Scheduling tests for VLSI systems under power constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Diagnostic testing of embedded memories using BIST
DATE '00 Proceedings of the conference on Design, automation and test in Europe
An integrated system-on-chip test framework
Proceedings of the conference on Design, automation and test in Europe
A Programmable BIST Core for Embedded DRAM
IEEE Design & Test
Embedded Software-Based Self-Test for Programmable Core-Based Designs
IEEE Design & Test
HIST: A Methodology for the Automatic Insertion of a Hierarchical Self Test
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Macro Testability: The Results of Production Device Applications
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Infrastructure IP for Configuration and Test of Boards and Systems
IEEE Design & Test
A built-in self-test and self-diagnosis scheme for embedded SRAM
ATS '00 Proceedings of the 9th Asian Test Symposium
Test Scheduling of BISTed Memory Cores for SOC
ATS '02 Proceedings of the 11th Asian Test Symposium
Efficient Wrapper/TAM Co-Optimization for Large SOCs
Proceedings of the conference on Design, automation and test in Europe
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Towards a Standard for Embedded Core Test: An Example
ITC '99 Proceedings of the 1999 IEEE International Test Conference
HD-BIST: A Hierarchical Framework for BIST Scheduling and Diagnosis in SoCs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques
Journal of Electronic Testing: Theory and Applications
New Challenges in Delay Testing of Nanometer, Multigigahertz Designs
IEEE Design & Test
A P1500-Compatible Programmable BIST Aapproach for the Test of Embedded Flash Memories
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
On the Automation of the Test Flow of Complex SoCs
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
An effective technique for minimizing the cost of processor software-based diagnosis in SoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Software-based self-test of processors under power constraints
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Systematic software-based self-test for pipelined processors
Proceedings of the 43rd annual Design Automation Conference
Simulation-Based Functional Test Generation for Embedded Processors
IEEE Transactions on Computers
Software-based self-testing methodology for processor cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Effective software-based self-test strategies for on-line periodic testing of embedded processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Guest editor's introduction: what is infrastructure IP?
IEEE Design & Test
| Hi-index | 0.00 |
During IC manufacturing phase, discriminating between good and faulty chips is not enough. In fact, especially in the first phase of the production of a new device, a complete understanding of the possible failures is quickly required to ramp up production yield. For test engineers, dealing with the manufacturing test of Systems-on-chip (SoCs) means to tackle the extraction of diagnostic data from faulty chips. Another equally important aim of diagnosis, in a later step of a product lifecycle, is to find the real root cause of silicon misbehaviors for field returns. At the core test layer, the adoption of diagnosis-oriented Design-for-Testability structures is almost mandatory and many solutions have been worked out for several types of cores; diagnosis data retrieval often consists in the execution of a set of self-test procedures whose application order and/or customization may depend on the obtained results themselves. This paper details the characteristics of a system-layer test architecture able to manage efficiently SoC self-diagnostic procedures. This architecture is composed of a diagnosis-oriented Test Access Mechanism (TAM) and an Infrastructure-IP owning enough intelligence to automatically manage core diagnostic procedures. Both of them have been designed in compliance with the IEEE 1500 Standard for Embedded Core Test and exploit the characteristics of Self-Test structures inserted for the diagnosis of memory, processor and logic cores. This approach to SoC diagnosis minimizes ATE memory requirements for pattern storage and drastically speeds up the complete execution of diagnostic procedures. Experimental results highlight the convenience of the approach with respect to alternative ATE driven diagnosis procedures, while resorting to negligible area overhead.