IEEE Transactions on Pattern Analysis and Machine Intelligence
Fault Diagnosis of RAMs from Random Testing Experiments
IEEE Transactions on Computers
Shapes Recognition Using the Straight Line Hough Transform: Theory and Generalization
IEEE Transactions on Pattern Analysis and Machine Intelligence
Diagnostic testing of embedded memories using BIST
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Memory fault diagnosis by syndrome compression
Proceedings of the conference on Design, automation and test in Europe
Error catch and analysis for semiconductor memories using march tests
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Built-In Self-Diagnosis for Repairable Embedded RAMs
IEEE Design & Test
A Programmable BIST Core for Embedded DRAM
IEEE Design & Test
Test and repair of large embedded DRAMs. 2
Proceedings of the IEEE International Test Conference 2001
Built in self repair for embedded high density SRAM
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A P1500 Compliant BIST-Based Approach to Embedded RAM Diagnosis
ATS '01 Proceedings of the 10th Asian Test Symposium
MTDT '96 Proceedings of the 1996 IEEE International Workshop on Memory Technology, Design and Testing (MTDT '96)
Towards a Standard for Embedded Core Test: An Example
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A fast globally optimal algorithm for template matching using low-resolution pruning
IEEE Transactions on Image Processing
A System-layer Infrastructure for SoC Diagnosis
Journal of Electronic Testing: Theory and Applications
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This paper proposes a new solution for the diagnosis of faults into embedded RAMs, currently under evaluation within STMicroelectronics. The proposed scheme uses dedicated circuitry embedded in a BIST wrapper, and an ATE test program to schedule the data extraction flow and to analyze the gathered information. Testing is performed exploiting a standard IEEE 1149.1 TAP, which allows the access to multiple memory cores with a P1500 compliant solution. The approach aims at implementing a low-cost solution to diagnose embedded RAMs with the goal to minimize the ATE costs and the time required to extract the diagnostic information. In our approach, the ATE drives the diagnostic scheme and performs the classification of faults, allowing the adoption of low-cost equipments. The proposed solution allows a scalable extraction of test data, whose amount is proportional to the available testing time. In order to accelerate fault classification, image processing techniques have been applied. The Hough transform has been adopted to analyze the bitmap representing the faulty cells. Experimental results show the advantages of the proposed approach in terms of time required to complete the diagnostic process.