Serial Interfacing for Embedded-Memory Testing
IEEE Design & Test
Using March Tests to Test SRAMs
IEEE Design & Test
Built-In Self-Diagnosis for Repairable Embedded RAMs
IEEE Design & Test
Industrial BIST of Embedded RAMs
IEEE Design & Test
A D&T Roundtable: Testing Mixed Logic and DRAM Chips
IEEE Design & Test
IEEE Micro
Cost and benefit models for logic and memory BIST
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A programmable built-in self-test core for embedded memories
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Processor-programmable memory BIST for bus-connected embedded memories
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Simulation-based test algorithm generation and port scheduling for multi-port memories
Proceedings of the 38th annual Design Automation Conference
An on-chip march pattern generator for testing embedded memory cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM
Journal of Electronic Testing: Theory and Applications
A Novel Built-In Self-Repair Approach for Embedded RAMs
Journal of Electronic Testing: Theory and Applications
A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques
Journal of Electronic Testing: Theory and Applications
A P1500-Compatible Programmable BIST Aapproach for the Test of Embedded Flash Memories
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A System-layer Infrastructure for SoC Diagnosis
Journal of Electronic Testing: Theory and Applications
An accumulator-based compaction scheme for online BIST of RAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Fault models for embedded-DRAM macros
Proceedings of the 46th Annual Design Automation Conference
BIST design optimization for large-scale embedded memory cores
Proceedings of the 2009 International Conference on Computer-Aided Design
Diagnosis of MRAM write disturbance fault
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Testing methodology of embedded DRAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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With the advent of deep-submicron VLSI technology, ASIC vendors are turning toward the single-chip system solution which integrates cores from various sources. Memory is one of the most universal cores-almost all system chips contain some type of embedded memory. Embedded SRAM's have been widely used, since by merging memory with logic, data bandwidth can be increased and hardware cost can be reduced. Now, with multimillion-gate designs that are pad-limited, we can see why embedded DRAM is also becoming an attractive core to them. With the clear trend that embedded DRAM will play an important role in the IC market over the next few years, their testing is becoming an industry-wide concern. Built-in self-test (BIST) is widely considered to be the best way for functional testing of embedded DRAM's. In this paper, we propose a programmable embedded DRAM BIST scheme which supports various test modes using a simple controller. An EDO DRAM is used as an example to delineate our BIST design and implementation. A novel memory fault simulator also has been implemented and used to analyze the fault coverage of the test algorithms for our BIST design. Our analysis shows that, with the March C- algorithm, the BIST overhead is less than 1.3% for a 1Mb DRAM, and it drops to below 0.3% for a 16Mb DRAM. Also, since the proposed BIST design is programmable, it can easily be applied to other DRAM types.