Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Using March Tests to Test SRAMs
IEEE Design & Test
A Programmable BIST Core for Embedded DRAM
IEEE Design & Test
An extended march test algorithm for embedded memories
ATS '97 Proceedings of the 6th Asian Test Symposium
March PS(23N) Test for DRAM Pattern-Sensitive Faults
ATS '98 Proceedings of the 7th Asian Test Symposium
Hardware/Software Co-testing of Embedded Memories in Complex SOCs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
An accumulator-based compaction scheme for online BIST of RAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this correspondence, we propose an effective approach to integrate 40 existing march algorithms into an embedded low hardware overhead test pattern generator to test the various kinds of word-oriented memory cores. Each march algorithm is characterized by several sets of up/down address orders, read/write signals, read/write data, and lengths of read/write operations. These characteristics are stored on chip so that any desired march algorithm can be generated with very little external control. An efficient procedure to reduce the memory storage for these characteristics is presented. We use only two programmable cyclic shift registers to generate the various read/write signals and data within the steps of the algorithms. Therefore, the proposed pattern generator is capable of generating any march algorithm with small area overhead.