System-in-Package Testing: Problems and Solutions
IEEE Design & Test
A System-layer Infrastructure for SoC Diagnosis
Journal of Electronic Testing: Theory and Applications
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Modern Systems-on-Chip (SoCs) allow integrating many different functional cores in the same piece of silicon. Their test requires to take fast decisions in the selection of structures and strategies at different stages of the design flow: early computation of area overhead, power consumption and test application time are indispensable in order to develop effective and efficient test for the overall chip, while taking into account physical constraints imposed by the available test equipment. Furthermore, once the test strategy has been selected and patterns generated for each module, additional non-negligible effort is required to integrate the test program in an ATE-readable format. In this paper we tackle these problems by means of a new software platform, leveraging descriptions of both the core-level test structure and the system-level requirements. Experimental results related to a realistic case of study underline the effectiveness of the tool and its potentialities in the IEEE 1500 environments.