Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On the Automation of the Test Flow of Complex SoCs
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Practices in Mixed-Signal and RF IC Testing
IEEE Design & Test
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Testing Multilayer Flexible Wireless Multisensor Platforms
Journal of Electronic Testing: Theory and Applications
Hi-index | 0.00 |
Editor's note: System-in-package integrates multiple dies in a common package. Therefore, testing SiP technology is different from system-on-chip, which integrates multiple vendor parts. This article provides test strategies for known-good-die and known-good-substrate in the SiP. Case studies provefeasibility using the IEEE 1500 test structure.