Implementing Macro Test in Silicon Compiler Design
IEEE Design & Test
HIST: A Methodology for the Automatic Insertion of a Hierarchical Self Test
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded Cores
Proceedings of the IEEE International Test Conference
A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
A Programmable BIST Architecture for Clusters of Multiple-Port SRAMs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
On Integrating a Proprietary and a Commercial Architecture for Optimal BIST Performances in SoCs
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A System-layer Infrastructure for SoC Diagnosis
Journal of Electronic Testing: Theory and Applications
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This paper proposes HD-BIST, a complete frameworkto support the definition of the scheduling strategy andmechanism of the BISTed blocks of a complex system.Three different layers are presented, to define the HD-BISTapproach in terms of a set of high-level BIST schedulingprimitives, a communication protocol, and a possiblehardware implementation, respectively.