Scheduling tests for VLSI systems under power constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 39th annual Design Automation Conference
Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits
IEEE Transactions on Computers
On Concurrent Test of Core-Based SOC Design
Journal of Electronic Testing: Theory and Applications
Adaptive Test Scheduling in SoC's by Dynamic Partitioning
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Integrated Test Scheduling, Test Parallelization and TAMDesign
ATS '02 Proceedings of the 11th Asian Test Symposium
Recent Advances in Test Planning for Modular Testing of Core-Based SOCs
ATS '02 Proceedings of the 11th Asian Test Symposium
Reducing Test Power During Test Using Programmable Scan Chain Disable
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
Test Resource Partitioning and Optimization for SOC Designs
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Power Constrained Test Scheduling with Dynamically Varied TAM
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
An ILP Formulation to Optimize Test Access Mechanism in System-on-Chip Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D
ATS '01 Proceedings of the 10th Asian Test Symposium
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores
ATS '01 Proceedings of the 10th Asian Test Symposium
Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Test Power Reduction through Minimization of Scan Chain Transitions
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling
ETW '03 Proceedings of the 8th IEEE European Test Workshop
Power-Time Tradeoff in Test Scheduling for SoCs
ICCD '03 Proceedings of the 21st International Conference on Computer Design
SoC Test Scheduling with Power-Time Tradeoff and Hot Spot Avoidance
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Test scheduling for core-based systems using mixed-integer linear programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A unified approach to reduce SOC test data volume, scan power and testing time
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
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We present a comprehensive and flexible test scheduling environment, called FITS, for testing core-based system-on-chips. Our environment prevents formation of hot spots during test. It also allows trade-off among test time, test access mechanism, power, and test controller/resource constraints. The basic strategy is to use power profile over application time and structural grids of nonembedded cores to find the best test schedule of their test pattern subsets while satisfying the constraints. As case studies, four integer linear programming formulations, corresponding to four power approximation models, are extensively analyzed. With proper setting of the weights and constraints, optimized results can be obtained quickly for each of the four power approximation models. Extensive experimental results are reported based on ISCAS '89 benchmarks and verify the efficiency and flexibility of the FITS environment.