Scheduling tests for VLSI systems under power constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Power-Time Tradeoff in Test Scheduling for SoCs
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Test scheduling for core-based systems using mixed-integer linear programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FITS: An Integrated ILP-Based Test Scheduling Environment
IEEE Transactions on Computers
Model driven scheduling framework for multiprocessor soc design
PPAM'05 Proceedings of the 6th international conference on Parallel Processing and Applied Mathematics
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We present a test scheduling methodology for core-based system-on-chips that can avoid hot spots and allows tradeoff between physical power dissipation and overall test time. A mixed integer linear programming formulation is presented to globally perform the power-time tradeoff, satisfy constraints, and produce the SoC test schedule.