Power-Time Tradeoff in Test Scheduling for SoCs

Authors:
Mehrdad Nourani;James Chin
Affiliations:
-;-
Venue:
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Year:
2003

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Abstract

We present a test scheduling methodology for core-basedsystem-on-chips that allows tradeoff between system powerdissipation and overall test time. The basic strategy is to use thepower profile of non-embedded cores to find the best mix of theirtest pattern subsets that satisfy the power and/or timeconstraints. An MILP formulation is presented to globally performthe power-time tradeoff and produce the SoC test schedule. Manyconstraints including peak/average power of cores, time/sequencingrequirements, and ATE pin limitation are also incorporated withinthis formulation.