Integrated Test Scheduling, Test Parallelization and TAMDesign

Authors:
Erik Larsson;Klas Arvidsson;Hideo Fujiwara;Zebo Peng
Affiliations:
Nara Institute of Science and Technology and Linköpings Universitet, Linköping, Sweden;Linköpings Universitet, Linköping, Sweden;Nara Institute of Science and Technology;Linköpings Universitet, Linköping, Sweden
Venue:
ATS '02 Proceedings of the 11th Asian Test Symposium
Year:
2002

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Abstract

We propose a technique integrating test scheduling, scanchain partitioning and test access mechanism (TAM) designminimizing the test time and the TAM routing cost whileconsidering test conflicts and power constraints. Mainfeatures of our technique are (1) the flexibility in modellingthe systems test behaviour and (2) the support forinterconnection test of unwrapped cores and user-definedlogic. Experiments using our implementation on severalbenchmarks and industrial designs demonstrate that itproduces high quality solution at low computational cost.