Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ATPG for Heat Dissipation Minimization During Test Application
IEEE Transactions on Computers
Low Power Design in Deep Submicron Electronics
Low Power Design in Deep Submicron Electronics
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
20.3 A Test Pattern Generation Methodology for Low-Power Consumption
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Graph theory: An algorithmic approach (Computer science and applied mathematics)
Graph theory: An algorithmic approach (Computer science and applied mathematics)
Power management using test-pattern ordering for wafer-level test during burn-in
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A question is considered as to the development of a procedure of testing combinational circuits with due regard for the power consumed during tests. It is shown that in the general case, the optimization problem of the consumable energy reduces to the known problem of discrete mathematics—the traveling salesman problem.