Scheduling tests for VLSI systems under power constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Optimization Trade-offs for Vector Volume and Test Power
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Reducing Power Dissipation during Test Using Scan Chain Disable
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
LT-RTPG: A New Test-Per-Scan BIST TPG for Low Heat Dissipation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Power consumption during scan testing is becoming a concern. Circuit switching activity during scanshifting is high and results in high average and instantaneous power consumption. This paper presentsa scheme for reducing power and provides analysis results on an industrial design.