Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Low power realization of finite state machines—a decomposition approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scheduling tests for VLSI systems under power constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Effects of delay models on peak power estimation of VLSI sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
ATPG for Heat Dissipation Minimization During Test Application
IEEE Transactions on Computers
Power management in high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Two-level logic minimization for low power
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low Power Digital CMOS Design
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An approach for multilevel logic optimization targeting low power
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power buffered clock tree design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Probabilistic modeling of dependencies during switching activity analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power state assignment targeting two- and multilevel logic implementations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
An Analysis of Powe Reduction Techniques in Scan Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Testability Trade-Offs for BIST Data Paths
Journal of Electronic Testing: Theory and Applications
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A critical-path-aware partial gating approach for test power reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Journal of Electronic Testing: Theory and Applications
Low power Illinois scan architecture for simultaneous power and test data volume reduction
Proceedings of the conference on Design, automation and test in Europe
Hi-index | 0.01 |