Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
On identifying don't care inputs of test patterns for combinational circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation
Proceedings of the IEEE International Test Conference on Test and Design Validity
Low Power BIST by Filtering Non-Detecting Vectors
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
Low-Energy BIST Design for Scan-based Logic Circuits
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A Test Vector Inhibiting Technique for Low Energy BIST Design
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Low Power BIST via Non-Linear Hybrid Cellular Automata
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
A New Reseeding Technique for LFSR-Based Test Pattern Generation
IOLTW '01 Proceedings of the Seventh International On-Line Testing Workshop
Low Power BIST with Smoother and Scan-Chain Reorder
ATS '04 Proceedings of the 13th Asian Test Symposium
On Finding Consecutive Test Vectors in a Random Sequence for Energy-Aware BIST Design
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
MICRO: a new hybrid test data compression/ decompression scheme
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient BIST TPG design and test set compaction via input reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Relationship Between Entropy and Test Data Compression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test patterns of multiple SIC vectors: theory and application in BIST schemes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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To tackle with the increased switching activity during the test operation, this paper proposes a new built-in self test (BIST) scheme for low energy testing that uses a statistical code and a new technique to skip unnecessary test sequences. From a general point of view, the goal of this technique is to minimize the total power consumption during a test and to allow the at-speed test in order to achieve high fault coverage. The effectiveness of the proposed low energy BIST scheme was validated on a set of ISCAS '89 benchmark circuits with respect to test data volume and energy saving.