MICRO: a new hybrid test data compression/ decompression scheme

Authors:
Sunghoon Chun;YongJoon Kim;Jung-Been Im;Sungho Kang
Affiliations:
Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea;Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea;Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea;Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2006

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Abstract

To overcome the limitation of the automatic test equipment (ATE), test data compression/decompression schemes become a more important issue of testing for a system-on-chip (SoC). In order to alleviate the limitation of previous works, a new hybrid test data compression/decompression scheme for an SoC is developed. The new scheme is based on analyzing the factors that influence test parameters: compression ratio and hardware overhead. To improve compression ratio, the proposed scheme, called the Modified Input reduction and CompRessing One block (MICRO), uses the modified input reduction, the one block compression, a novel mapping, and reordering algorithms. Unlike previous approaches using the cyclic scan register architecture, the proposed scheme is to compress original test data and to decompress the compressed test data without the cyclic scan register architecture. Therefore, the proposed scheme leads to high-compression ratio with low-hardware overhead. Experimental results on ISCAS '89 and ITC '99 benchmark circuits prove the efficiency of the new method.