Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A synthesis-for-transparency approach for hierarchical and system-on-a-chip test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Embedded Deterministic Test for Low-Cost Manufacturing
IEEE Design & Test
IEEE Transactions on Computers
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hardware Ef.cient LBISTWith Complementary Weights
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Study on Expansion of Convolutional Compactors over Galois Field
IEICE - Transactions on Information and Systems
Study on Test Data Reduction Combining Illinois Scan and Bit Flipping
IEICE - Transactions on Information and Systems
Improving compressed test pattern generation for multiple scan chain failure diagnosis
Proceedings of the Conference on Design, Automation and Test in Europe
MICRO: a new hybrid test data compression/ decompression scheme
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a new technique, called C-compatibility, for reducing the test application time of the counter-based exhaustive Built-in-Self-Test (BIST) test pattern generators. This technique reduces the test application time by reducing the size of the binary counter used in the test pattern generators. We have incorporated the synthesis algorithm for synthesizing BIST test pattern generators using the C-compatibility technique into ATOM, an advanced ATPG system for combinational circuits. The experimental results showed that the test pattern generators synthesized using this technique for the ISCAS85 and full scan versions of the ISCAS89 benchmark circuits achieve 100% stuck-at fault coverage in much smaller test application time than the previously published counter-based exhaustive BIST test pattern generators.