Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
STARBIST: scan autocorrelated random pattern generation
DAC '97 Proceedings of the 34th annual Design Automation Conference
ScanBist: A Multifrequency Scan-Based BIST Method
IEEE Design & Test
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
REDUCING TEST DATA VOLUME USING EXTERNAL/LBIST HYBRID TEST PATTERNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '04 Proceedings of the International Test Conference on International Test Conference
Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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Convolutional compactors offer a promising technique of compacting test responses. In this study we expand the architecture of convolutional compactor onto a Galois field in order to improve compaction ratio as well as reduce X-masking probability, namely, the probability that an error is masked by unknown values. While each scan chain is independently connected by EOR gates in the conventional arrangement, the proposed scheme treats q signals as an element over GF(2q), and the connections are configured on the same field. We show the arrangement of the proposed compactors and the equivalent expression over GF(2). We then evaluate the effectiveness of the proposed expansion in terms of X-masking probability by simulations with uniform distribution of X-values, as well as reduction of hardware overheads. Furthermore, we evaluate a multi-weight arrangement of the proposed compactors for non-uniform X distributions.