Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Accelerated transition fault simulation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Delay Test: The Next Frontier for LSSD Test Systems
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Skewed-Load Transition Test: Part 2, Coverage
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Application of Deterministic Logic BIST on Industrial Circuits
Journal of Electronic Testing: Theory and Applications
Instruction Randomization Self Test For Processor Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Bridging the Gap Between Embedded Test and ATE
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Application of Deterministic Logic BIST on Industrial Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
TREE-STRUCTURED LINEAR CELLULAR AUTOMATA AND THEIR APPLICATIONS AS PRPGS
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Testability Evaluation of Sequential Designs Incorporating the Multi-Mode Scannable Memory Element
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Achieving At-Speed Structural Test
IEEE Design & Test
Wrapper Design for Testing IP Cores with Multiple Clock Domains
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A seed selection procedure for LFSR-based random pattern generators
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Study on Expansion of Convolutional Compactors over Galois Field
IEICE - Transactions on Information and Systems
Study on Test Data Reduction Combining Illinois Scan and Bit Flipping
IEICE - Transactions on Information and Systems
Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate
IEICE - Transactions on Information and Systems
Do you practice safe test? what we found out about your habits
ITC'94 Proceedings of the 1994 international conference on Test
Wrapper design for multifrequency IP cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The authors present ScanBist, a low-overhead, scan-based built-in self-test method, along with its performance in several designs. A novel clock synchronization scheme allows at-speed testing of circuits. This design allows the testing of circuits operating at more than one frequency while retaining the combinational character of the circuit to be analyzed. We can therefore apply scan patterns that will exercise the circuit under test at the system speed, potentially providing a better coverage of delay faults when compared to other self-test methods. Modifications to an existing transition fault simulator account for cases where inputs originating from scan registers clocked at different frequencies drive a gate. We claim to detect transition faults only if the transition originates from the inputs driven by the highest frequency clock. ScanBist is useful at all levels of system packaging assuming that a standard TAP provides the control and boundary scan isolates the circuit from primary inputs and outputs during BIST mode.