ScanBist: A Multifrequency Scan-Based BIST Method
IEEE Design & Test
Structured Design-for-Debug - The SuperSPARCTM II Methodology and Implementation
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Scan Latch Design for Delay Test
Proceedings of the IEEE International Test Conference
Testing the 400-MHz IBM Generation-4 CMOS Chip
Proceedings of the IEEE International Test Conference
Synthesizing for Scan Dependence in Built-In Self-Testable Designs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A BIST Structure to Test Delay Faults in a Scan Environment
ATS '98 Proceedings of the 7th Asian Test Symposium
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
15.1 A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A Case Study of the Test Development for the 2nd Generation ColdFire® Microprocessors
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Multiple Scan Chain Design for Two-Pattern Testing
Journal of Electronic Testing: Theory and Applications
Multimode scan: Test per clock BIST for IP cores
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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The Multi-Mode Scannable Memory Element(MSME) is a design-for-test technique that combinesthe testing efficiency of the Circular Self-Test Path approach with a full scan capability to support customtest vectors, diagnosis, and design debugging. A keyfeature is the ability to support pseudorandom at-speeddelay testing of the functional circuit paths without imposing any performance penalty on the design beyondthat for traditional scan. This paper presents a CMOSdesign for the MSME, and investigates benchmark circuits designed with this memory element. The resultsshow that very high stuck-at and transition delay testcoverage can be achieved for most cases using the pseudorandom self-test mode alone. Evaluation of layoutsindicates low to moderate area overhead.