Pseudorandom arrays for built-in tests
Artificial Intelligence
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A method for generating weighted random test pattern
IBM Journal of Research and Development
Design considerations for parallel pseudorandom pattern generators
Journal of Electronic Testing: Theory and Applications
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
IEEE Spectrum
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
ScanBist: A Multifrequency Scan-Based BIST Method
IEEE Design & Test
Constructive Multi-Phase Test Point Insertion for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Using BIST Control for Pattern Generation
Proceedings of the IEEE International Test Conference
Deterministic BIST with multiple scan chains
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Automated synthesis of large phase shifters for built-in self-test
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Deterministic BIST with Partial Scan
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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We present the application of a deterministic logic BIST scheme based on bit-flipping on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100 K gates with 10,000 test patterns, at a total area cost for BIST hardware of typically 5–15%. It is demonstrated that a trade-off is possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required, complete fault efficiency is guaranteed, and the impact on the design process is minimized.