A deterministic approach to adjacency testing for delay faults
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Parallel pattern fault simulation of path delay faults
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Correlation-reduced scan-path design to improve delay fault coverage
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Quality Determination for Gate Delay Fault Tests Considering Three-State Elements
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Boundary Scan with Built-In Self-Test
IEEE Design & Test
ScanBist: A Multifrequency Scan-Based BIST Method
IEEE Design & Test
Robust and Nonrobust Path Delay Fault Simulation by Parallel Processing of Patterns
IEEE Transactions on Computers
Generation of tenacious tests for small gate delay faults in combinational circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
DFSIM: A Gate-Delay Fault Simulator for Sequential Circuits
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Testing High Speed VLSI Devices Using Slower Testers
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors
Journal of Electronic Testing: Theory and Applications
On the fault coverage of delay fault detecting tests
EURO-DAC '90 Proceedings of the conference on European design automation
Functions for Quality Transition Fault Tests
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Test set enhancement for quality transition faults using function-based methods
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Scaling of iDDT Test Methods for Random Logic Circuits
Journal of Electronic Testing: Theory and Applications
Boundary scan with cellular-based built-in self-test
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Stuck-open and transition fault testing in CMOS complex gates
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
On the detection of delay faults
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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This paper presents a new and an effective approach to fault simulation of transition faults in combinational or scan - based logic. An experiment with a set of benchmark circuits demonstrates the efficiency of the approach, achieved by combining a very fast single stuck - at fault simulation algorithm with a quasi - static definition of a transition fault. Tests that cover transition faults are becoming increasingly important as they also provide a cover for most typical transistor stuck - open faults in CMOS.