Accelerated transition fault simulation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Path hashing to accelerate delay fault simulation
DAC '94 Proceedings of the 31st annual Design Automation Conference
New methods of improving parallel fault simulation in synchronous sequential circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A Statistical Model for Delay-Fault Testing
IEEE Design & Test
Robust and Nonrobust Path Delay Fault Simulation by Parallel Processing of Patterns
IEEE Transactions on Computers
Robustness Enhancement and Detection Threshold Reduction in ATPG for Gate Delay Faults
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Gate delay fault test generation for non-scan circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
DAC '77 Proceedings of the 14th Design Automation Conference
Consistently dominant fault model for tristate buffer nets
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Testing "untestable" faults in three-state circuits
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
| Hi-index | 0.00 |
This paper describes a test method for analogue (partsof) ICs that determines whether an IC is good or not bymeasuring the currents flowing through its constituent circuits.The ICCQ test method is not a full functional test. Itis aimed primarily ...