Quality Determination for Gate Delay Fault Tests Considering Three-State Elements
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Using ATPG for clock rules checking in complex scan designs
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
OPTIMIZING THE FLATTENED TEST-GENERATION MODEL FOR VERY LARGE DESIGNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
How Seriously Do You Take Possible-Detect Faults?
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Modeling Custom Digital Circuits for Test
Journal of Electronic Testing: Theory and Applications
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High-performance, complex CMOS designs such as microprocessors continue to gain performance by the use of "non-conventional" circuits such as tri-state, ratio or precharged logic. Such circuits are also used in noncomplementary or DC-redundant structures. While such design styles are not really new, their widespread use in very large, complex circuits (e.g., microprocessors) make "conventional" fault modeling and test generation ineffective. This paper describes test generation techniques to handle such circuits without affecting their performance or area. These techniques exploit circuit particularities of noncomplementary CMOS design in fault modeling, use automatic learning of useful relations about nodes in the design, and innovative test vector generation. On several designs ranging up to 2.5 million gates, the combined application of these methods increased test coverage from 50% to 100% while decreasing CPU time by orders of magnitude.