Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Accelerated transition fault simulation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Test Generation for Path Delay Faults Using Binary Decision Diagrams
IEEE Transactions on Computers
Compact two-pattern test set generation for combinational and full scan circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On Generating High Quality Tests for Transition Faults
ATS '02 Proceedings of the 11th Asian Test Symposium
TranGen: a SAT-based ATPG for path-oriented transition faults
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Functions for Quality Transition Fault Tests
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Classification and identification of nonrobust untestable path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A recent method generates high quality tests for transition faults using functions. Event sensitization criteria as well as path lengths can be taken into consideration during the generation of such test functions. It is shown how to manipulate the test functions to generate compact test sets. Experimental results on ISCAS'85 and ISCAS'89 circuits show that a compaction rate of the order of 70% to 84% is achieved without compromising fault coverage. Moreover, a novel method to enrich the compacted test set with additional vectors is presented so that transition faults are tested through different activation and propagation paths. Such test sets havehigher quality, compared to traditional transition fault test sets, since events propagate through many critical paths.