Proceedings of the 39th annual Design Automation Conference
Test of future system-on-chips
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
ScanBist: A Multifrequency Scan-Based BIST Method
IEEE Design & Test
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test and debug strategy of the PNX8525 NexperiaTM digital video platform system chip
Proceedings of the IEEE International Test Conference 2001
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Wrapper Design for Embedded Core Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Multi-frequency wrapper design and optimization for embedded cores under average power constraints
Proceedings of the 42nd annual Design Automation Conference
Power-constrained test scheduling for multi-clock domain SoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A flexible and scalable methodology for GHz-speed structural test
Proceedings of the 43rd annual Design Automation Conference
Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints
IEICE - Transactions on Information and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper addresses the testability problems raised by embedded cores with multiple clock domains. The proposed solution, based on a novel core wrapper architecture, shows how multi-frequency at-speed test response capture can be achieved using low-speed testers synchronized with high-speed on-chip generated clocks. Using experimental data, the trade-offs between the number of tester channels, testing time, area overhead and power dissipation are discussed.