A flexible and scalable methodology for GHz-speed structural test

Authors:
Vikram Iyengar;Gary Grise;Mark Taylor
Affiliations:
IBM Microelectronics, Essex Junction, VT;IBM Microelectronics, Essex Junction, VT;IBM Microelectronics, Essex Junction, VT
Venue:
Proceedings of the 43rd annual Design Automation Conference
Year:
2006

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Abstract

At-speed test of integrated circuits is becoming critical to detect subtle delay defects. Simulation-based functional test is difficult because low-cost testers are unable to supply multiple asynchronous clocks to the IC. Moreover, low-cost testers simply cannot operate at chip speed. Existing structural at-speed test methods are inadequate because they are unable to supply sufficiently-varied functional clock sequences to test complex sequential logic. Moreover, they require tight restrictions on the circuit design. In this paper, we present a new method for GHz-speed structural test of ASICs having no tight restrictions on the circuit design. In the present implementation, any complex at-speed functional clock waveform for 16 cycles can be applied. We also describe a method to test asynchronous clock domains simultaneously. Experimental results for two multi-million gate ASICs demonstrate high at-speed coverage.