The Testability Features of the 3rd Generation Coldfire® Family of Microprocessors
ITC '99 Proceedings of the 1999 IEEE International Test Conference
MODELING AND TESTING THE GEKKO MICROPROCESSOR, AN IBM POWERPC DERIVATIVE FOR NINTENDO
ITC '01 Proceedings of the 2001 IEEE International Test Conference
AC Scan Path Selection for Physical Debugging
IEEE Design & Test
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Performance verification of high-performance ASICs using at-speed structural test
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A flexible and scalable methodology for GHz-speed structural test
Proceedings of the 43rd annual Design Automation Conference
An on-chip clock generation scheme for faster-than-at-speed delay testing
Proceedings of the Conference on Design, Automation and Test in Europe
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The DFT and Test challenges faced, and the solutionsapplied, to the newest member of the ColdFire®microprocessor family, the MCF5407, are describedin this paper. The MCF5407 is the first member of thefamily to utilize a PLL-sourced clock to do at-speedlaunch-to-capture cycles. This PLL-sourced testclock can be "chopped" in any manner needed forcore to asic ratios between 4:1 and 1:1. The internalmicroprocessor core of the MCF5407 was designedas a separate stand-alone core. The DFT challengesand solutions described in this paper involve thechallenges that are above and beyond the challengesof the MCF5307; including the PLL clock chop andenhanced PLL scan testing.