THE TESTABILITY FEATURES OF THE MCF5407 CONTAINING THE 4TH GENERATION COLDFIRE® MICROPROCESSOR CORE
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Reducing Pattern Delay Variations for Screening Frequency Dependent Defects
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
On Hazard-free Patterns for Fine-delay Fault Testing
ITC '04 Proceedings of the International Test Conference on International Test Conference
ALAPTF: A NEW TRANSITION FAULTMODEL AND THE ATPG ALGORITHM
ITC '04 Proceedings of the International Test Conference on International Test Conference
Timing-based delay test for screening small delay defects
Proceedings of the 43rd annual Design Automation Conference
A novel framework for faster-than-at-speed delay test considering IR-drop effects
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs
Journal of Electronic Testing: Theory and Applications
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Faster-than-at-speed testing provides an effective way for detecting and debugging small delay defects in modern fabricated chips. However, the use of external automatic test equipment for faster-than-at-speed delay testing could be costly. In this paper, we present an on-chip clock generation scheme which facilitates faster-than-at-speed delay testing for both launch on capture and launch on shift test frameworks. The required test clock frequency with a high resolution can be obtained by specifying the information in the test patterns, which is then shifted into the delay control stages to configure the launch and capture clock generation circuit (LCCG) embedded on-chip. Similarly, the control information for selecting various test frameworks and clock signals can also be embedded in the test patterns. Experimental results are presented to validate the proposed scheme.