Very-Low-Voltage Testing for Weak CMOS Logic ICs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Scan-Based Transition Fault Testing " Implementation and Low Cost Test Challenges
ITC '02 Proceedings of the 2002 IEEE International Test Conference
High-Frequency, At-Speed Scan Testing
IEEE Design & Test
Reducing Pattern Delay Variations for Screening Frequency Dependent Defects
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
At-Speed Transition Fault Testing With Low Speed Scan Enable
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
On Hazard-free Patterns for Fine-delay Fault Testing
ITC '04 Proceedings of the International Test Conference on International Test Conference
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits
ITC '04 Proceedings of the International Test Conference on International Test Conference
ALAPTF: A NEW TRANSITION FAULTMODEL AND THE ATPG ALGORITHM
ITC '04 Proceedings of the International Test Conference on International Test Conference
Transition delay fault test pattern generation considering supply voltage noise in a SOC design
Proceedings of the 44th annual Design Automation Conference
Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
X-align: improving the scan cell observability of response compactors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An on-chip clock generation scheme for faster-than-at-speed delay testing
Proceedings of the Conference on Design, Automation and Test in Europe
A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test
Proceedings of the Conference on Design, Automation and Test in Europe
A physical-location-aware fault redistribution for maximum IR-drop reduction
Proceedings of the 16th Asia and South Pacific Design Automation Conference
A physical-location-aware X-bit redistribution for maximum IR-drop reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high-precision on-chip path delay measurement architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Faster-than-at-speed test have been proposed to detect small delay defects. While these techniques increase the test frequency to reduce the positive slack of the path, they exacerbate the already well known issue of IR-drop during test. This may result in false identification of good chips to be faulty due to IR-drop rather than small delay defects. We present a case study of IR-drop effects due to faster-than-at-speed test. We propose a novel framework for pattern generation/application using any commercial no-timing ATPG tool, to screen small delay defects and a technique to determine the optimal test frequency considering both performance degradation due to IR-drop effects and positive slack.