A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Improving Transition Delay Test Using a Hybrid Method
IEEE Design & Test
A novel framework for faster-than-at-speed delay test considering IR-drop effects
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Transition delay fault test pattern generation considering supply voltage noise in a SOC design
Proceedings of the 44th annual Design Automation Conference
Controllability of Static CMOS Circuits for Timing Characterization
Journal of Electronic Testing: Theory and Applications
A novel faster-than-at-speed transition-delay test method considering IR-drop effects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level test synthesis with hierarchical test generation for delay-fault testability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power
Journal of Electronic Testing: Theory and Applications
Improved launch for higher TDF coverage with fewer test patterns
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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With today's design size in millions of gates and working frequency in gigahertz range, at-speed test is crucial. The launch-off-shift method has several advantages over the launch-off-capture but imposes strict requirements on transition fault testing due to at-speed scan enable signal. A novel scan-based at-speed test is proposed which generates multiple local fast scan enable signals. The scan enable control information is encapsulated in the test data and transferred during the scan operation. A new scan cell, referred to as last transition generator (LTG), is inserted in the scan chains to generate the fast local scan enable signal. The proposed technique is robust, practice-oriented and suitable for use in an industrial flow.