A method of delay fault test generation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Skewed-Load Transition Test: Part 1, Calculus
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
On Achieving Complete Coverage of Delay Faults in Full Scan Circuits using Locally Available Lines
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Proceedings of the conference on Design, automation and test in Europe - Volume 2
At-Speed Transition Fault Testing With Low Speed Scan Enable
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Improved launch for higher TDF coverage with fewer test patterns
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Electronic Testing: Theory and Applications
Hi-index | 0.00 |
We propose a novel delay test method for achieving higher delay fault coverage. Multiple scan enable signals are used none of which require the ability to switch at-speed between launch and capture cycles.