DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A method of delay fault test generation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
DAC '77 Proceedings of the 14th Design Automation Conference
Designing CMOS Circuits for Switch-Level Testability
IEEE Design & Test
An Experimental Delay Test Generator for LSI Logic
IEEE Transactions on Computers
A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A robust pulsed flip-flop and its use in enhanced scan design
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
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This paper addresses the problem of testing for delay faults in sequential circuits which incorporate standard scan path design. The technique presented here aims at the reduction or elimination of enhanced-scan flip-flops and their associated overhead. Flip-flop sharing modifies the order of the flip-flops in the scan path such that adjacent flip-flops along the path are from different sequential machines. This allows the application of arbitrary two-vector test sets necessary for delay fault testing. This arrangement is feasible for practical circuits because today's complex ICs consist, in general, of many sequential machines that may need to be delay testable.