A robust pulsed flip-flop and its use in enhanced scan design

Authors:
Rajesh Kumar;Kalyana C. Bollapalli;Rajesh Garg;Tarun Soni;Sunil P. Khatri
Affiliations:
Department of ECE, Texas A&M University, College Station, TX;Department of ECE, Texas A&M University, College Station, TX;Intel Corporation, Hillsboro, OR;Department of ECE, Texas A&M University, College Station, TX;Department of ECE, Texas A&M University, College Station, TX
Venue:
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Year:
2009

Citing 6
Cited 1

Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits

ATS '95 Proceedings of the 4th Asian Test Symposium
Performance Comparison of Dynamic Voltage Scaling Algorithms for Hard Real-Time Systems

RTAS '02 Proceedings of the Eighth IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'02)
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Low Cost Launch-on-Shift Delay Test with Slow Scan Enable

ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
Improving the transition fault coverage of functional broadside tests by observation point insertion

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

Pulse width allocation and clock skew scheduling: optimizing sequential circuits based on pulsed latches

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Delay faults are frequently encountered in nanometer technologies. Therefore, it is critical to detect these faults during factory test. Testing for a delay fault requires the application of a pair of test vectors in an at-speed manner. To maximize the delay fault detection capability, it is desired that the vectors in this pair are independent. Independent vector pairs cannot always be applied to a circuit implemented with standard scan design approaches. However, this can be achieved by using enhanced scan flip-flops, which store two bits of data. This paper has two contributions. First, we develop a pulsed flip-flop (PFF) design. Second, we present an enhanced scan flip-flop design, based on our PFF circuit. We have compared the performance of our pulse based flip-flop with recently published pulse based flip-flop designs, as well as a traditional master-slave D flip-flop. Our PFF shows significant improvements in power and timing compared to the other designs. Our pulse based enhanced scan flip-flop (PESFF) has 13% lower power dissipation and 26% better timing than a conventional D flip-flop based enhanced scan flip-flop (DESFF). The layout area of our PESFF is 5.2% smaller than the DESFF. Monte Carlo simulations demonstrate that our design is more robust to process variations than the DESFF.