DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
At-Speed Test is not Necessarily an AC Test
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Skewed-Load Transition Test: Part 1, Calculus
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Skewed-Load Transition Test: Part 2, Coverage
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
IEEE Design & Test
Fastpath: a path-delay test generator for standard scan designs
ITC'94 Proceedings of the 1994 international conference on Test
On path delay testing in a standard scan environment
ITC'94 Proceedings of the 1994 international conference on Test
Compact test sets for high defect coverage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Conflict driven scan chain configuration for high transition fault coverage and low test power
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A novel test application scheme for high transition fault coverage and low test cost
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Design-for-testability for multi-cycle broadside tests by holding of state variables
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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We propose a testability enhancement technique for delayfaults in standard scan circuits that does not involve modificationsto the scan chain. Extra logic is placed on next-statevariables, and if necessary, on primary inputs, andcan be resynthesized with the circuit to minimize its hardwareand performance overheads. The proposed techniqueallows us to achieve complete coverage of detectabledelay faults. A simple test generation procedure that guaranteescomplete coverage when used with the proposedtechnique is also described.