Evolving effective CA/CSTP: BIST architectures for sequential circuits
Proceedings of the 2001 ACM symposium on Applied computing
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes
Proceedings of the 39th annual Design Automation Conference
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Scalable Delay Fault BIST for Use with Low-Cost ATE
Journal of Electronic Testing: Theory and Applications
Pseudorandom Test Pattern Generators for Built-in Self-Testing: A Power Reduction Method
Automation and Remote Control
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level
Journal of Electronic Testing: Theory and Applications
A Gated Clock Scheme for Low Power Testing of Logic Cores
Journal of Electronic Testing: Theory and Applications
A BIST TPG for low power dissipation and high fault coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new low energy BIST using a statistical code
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Suitability of various low-power testing techniques for IP core-based SoC: a survey
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
An Optimized Seed-based Pseudo-random Test Pattern Generator: Theory and Implementation
Journal of Electronic Testing: Theory and Applications
Test patterns of multiple SIC vectors: theory and application in BIST schemes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.01 |
In the last decade, researchers devoted many efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption during test operation mode was usually neglected. However, during test application circuits are subject to an activity level higher than the normal one: the extra power consumption due to test application may thus raise severe hazards to the circuit reliability. Moreover, it can dramatically shorten battery life when periodic testing of battery-powered systems is considered.In this paper, we propose an algorithm to design a Test Pattern Generator based on Cellular Automata for testing combinational circuits that effectively reduces power consumption while attaining high Fault Coverage. Experimental results show that our approach reduces the power consumed during test by 34% on the average, without affecting Fault Coverage, Test Length and area overhead.