Discrete logarithms: a parallel pseudorandom pattern generator analysis method
Journal of Electronic Testing: Theory and Applications
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power Characterization of LFSRs
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
A New BIST Architecture for Low Power Circuits
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
A Test Vector Inhibiting Technique for Low Energy BIST Design
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Low Power BIST via Non-Linear Hybrid Cellular Automata
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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A method of reducing the power consumption of a pseudorandom test pattern generator for scan-based built-in self-tests of digital devices is designed on the basis of formation of several test symbols in one operation cycle of the circuit.A new structure for low-power test pattern generators is described.