Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Pseudorandom Test Pattern Generators for Built-in Self-Testing: A Power Reduction Method
Automation and Remote Control
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This paper presents a formal analysis on the power consumption of BIST architectures composed of primitive-polynomial LFSRs connected to a combinational CUT. An exact power characterization of all primitive-polynomial LFSRs has been identified, since interesting invariant properties have been discovered.