A New BIST Architecture for Low Power Circuits

Authors:
F. Corno;M. Rebaudengo;M. Sonza Reorda;M. Violante
Affiliations:
-;-;-;-
Venue:
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
Year:
1999

Citing 0
Cited 7

Power-/Energy Efficient BIST Schemes for Processor Data Paths

IEEE Design & Test
Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths

ITC '00 Proceedings of the 2000 IEEE International Test Conference
Concurrent Scan Monitoring and Multi-Pattern Search

IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Pseudorandom Test Pattern Generators for Built-in Self-Testing: A Power Reduction Method

Automation and Remote Control
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level

Journal of Electronic Testing: Theory and Applications
System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability
Test patterns of multiple SIC vectors: theory and application in BIST schemes

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

Linear Feedback Shift Registers (LFSRs) are commonly used as pseudo-random test pattern generators (TPGs) in BIST schemes. This paper presents a fast simulation-based method to compute an efficient seed (initial state) of a given primitive polynomial ...