Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface
Journal of Electronic Testing: Theory and Applications
A Novel Method to Improve the Test Efficiency of VLSI Tests
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Low-Energy BIST Design for Scan-based Logic Circuits
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
SPaRe: Selective Partial Replication for Concurrent Fault Detection in FSMs
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Exploiting Ghost-FSMs as a BIST Structure for Sequential Machines
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Universal Test Generation Using Fault Tuples
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test vector decomposition-based static compaction algorithms for combinational circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Cost-Driven Selection of Parity Trees
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Fault simulation and random test generation for speed-independent circuits
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Journal of Electronic Testing: Theory and Applications
The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Efficient BIST design for sequential machines using FiF-FoF values in machine states
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
VFSim: concurrent fault simulation at register transfer level
Journal of Computer Science and Technology
High-level test synthesis for delay fault testability
Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Reducing test application time, test data volume and test power through Virtual Chain Partition
Integration, the VLSI Journal
A test set embedding approach based on twisted-ring counter with few seeds
Integration, the VLSI Journal
Fast enhancement of validation test sets for improving the stuck-at fault coverage of RTL circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test data compression using interval broadcast scan for embedded cores
Microelectronics Journal
Integration, the VLSI Journal
Diagnostic Test Set Minimization and Full-Response Fault Dictionary
Journal of Electronic Testing: Theory and Applications
Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints
Journal of Electronic Testing: Theory and Applications
Is split manufacturing secure?
Proceedings of the Conference on Design, Automation and Test in Europe
Logic encryption: a fault analysis perspective
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Security analysis of integrated circuit camouflaging
Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security
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HOPE is an efficient parallel fault simulator for synchronous sequential circuits that employs the parallel version of the single fault propagation technique. HOPE is based on an earlier fault simulator railed PROOFS, which employs several heuristics to efficiently drop faults and to avoid simulation of many inactive faults. In this paper, we propose three new techniques that substantially speed up parallel fault simulation: (1) reduction of faults simulated in parallel through mapping nonstem faults to stem faults, (2) a new fault injection method called functional fault injection, and (3) a combination of a static fault ordering method and a dynamic fault ordering method. Based on our experiments, our fault simulator, HOPE, which incorporates the proposed techniques, is about 1.6 times faster than PROOFS for 16 benchmark circuits