A Novel Method to Improve the Test Efficiency of VLSI Tests

Authors:
Hailong Cui;Sharad C. Seth;Shashank K. Mehta
Affiliations:
Dept. of Computer Science and Engineering, University of Nebraska-Lincoln, Lincoln, NE;Dept. of Computer Science and Engineering, University of Nebraska-Lincoln, Lincoln, NE;School of Information Technology, Indian Institute of Technology, Bombay
Venue:
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Year:
2002

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Abstract

This paper considers reducing the cost of test application by permuting test vectors to improve their defect coverage. Algorithms for test reordering are developed with the goal of minimizing the test cost. Best and worst case bounds are established for the performance of a reordered sequence compared to the original sequence of test application. SEMATECH test data and simulation results are used throughout to illustrate the ideas.